In the manufacture of complementary metal-oxide-silicon (CMOS) integrated circuits, it is known to provide multiple levels of aluminum on top of a silicon substrate and insulate these levels from one another with a dielectric layer such as silicon dioxide, SiO.sub.2. In order to interconnect these aluminum layers at selected circuit locations, holes or "vias" are etched in the silicon dioxide layer, and the upper layer of aluminum is deposited in part in these vias to make electrical connections with the lower aluminum layer. In this manner, separate circuitry may be provided for both P-channel and N-channel transistors or other devices which have been fabricated in the silicon substrate, as well known in the art.
One problem which arises in the above type of CMOS integrated circuit fabrication process is the formation of hillocks or spikes in the lower aluminum layer. In some cases, these hillocks or spikes are sufficiently large and sharp so as to completely penetrate the overlying silicon dioxide layer and provide an electrical short to the next level overlying aluminum layer.